1. Field of the Invention
This invention relates to a video signal processing apparatus employing the technique of digitizing the video signal.
2. Description of the Related Art
Recently, the digital technique has come to be applied even to the field of processing video signals. Particularly in the field of image instruments for use in offices, a wide variety of advantages has been enjoyed. The device for this digital image treatment has to be fabricated to a large scale and, therefore, becomes very expensive. For this reason, its introduction to instruments for public welfare such as home VTRs is in a very difficult situation.
That is, between the home and office instruments there a very large difference in the standard form of video signals, for the former deals with the composite television signals of the NTSC standards, and the latter with the component television signals, namely, either the R, G and B signals for the three primary colors, or the Y, I and Q signals for luminance and chrominances. As will be understood, to meet with the demand for a higher image quality and broader capabilities, the office instruments have employed the method of processing all informations in the form of the component television signals. Compared with the processing of all the informations in the form of the composite television signal, therefore, a far greater quantity of information must be processed. This leads to the necessity of a large increase in processing power per unit time and capacity of memory. From this reason, the necessary prerequisite for introduction of the digital image processing capability into the home instrument is to use the composite television signal when the processing to digital signals is performed, in other words, to carry out the direct encoding treatment. Further, for another treatments such as drop-out compensation or the like, in order to ensure continuity of the color subcarrier, an inverting circuit for the digital data becomes necessary.
The above-identified inverting circuit for the so-called chrominance signals has so far been designed on the principle shown in FIG. 1, where the chrominance signal of the video signal or the television signal of the NTSC standards is sampled at a rate of 4 times the frequency fsc of the color subcarrier or 4 fsc's. From among the sample data, a-e, of the chrominance signal, only the phase of the sample datum, c, is inverted. Hence, that inverted datum, c, is computed. Concretely speaking, the center value of the amplitude of the chrominance signal is regarded as the value of a line segment b-d as shown by a dashed line in the figure. Then, the inverted datum c is sought so that the position of bisecting the distance between the level of the inverted datum c and the sample datum c becomes the position of the above-described line segment b-d. And, on assumption that the correlativity of the signal lies near the sample datum c, the value of the inverted datum c is found as the mean value of the data a and e (c=(a+e)/2). Thus, to obtain the inverted datum c, it is necessary to perform addition of the data a and e once, and division of it once, in total, two computations.
FIG. 2 is a block diagram illustrating the circuit structure of the conventional video signal reproducing apparatus which performs computation based on the above-described formula. As has been described above, the inputted video signal is sampled at the frequency of 4 fsc's in synchronism with the color subcarrier, and this quantized digital video signal is applied to a 2-sample delay circuit 1. For the video signal not to be inverted, a selection switch circuit 2 allows the output of the delay circuit 1 to pass directly to an outlet. For the inverting purpose, on the other hand, the output of the first delay circuit 1 is applied to a second 2-sample delay circuit 3. Then, its output representing the video signal delayed 4 samples in total (corresponding to the datum e of FIG. 1) is added to the present signal (corresponding to the datum a of FIG. 1) by an adder 4. The output of this adder 4 is halved by the 1-bit shifting treatment in an divider 5. The thus-obtained datum is used as the inverted datum c of FIG. 1. The switch circuit 2 passes it to the outlet.
However, such a chrominance signal inverting circuit in the conventional video signal processing apparatus is, because of its having two computing treatments, associated with circuits of complicated structure. Hence, a problem arose that no simple form could be attained. Moreover, when processing the digital image informations, it is impossible with the composite television signal that its sampled data, without further alternation, are subjected to addition and subtraction. Hence another problem arose that the computing circuit and others were necessarily be formed to a large scale.
FIG. 3 also illustrates the circuit structure of the conventional video signal processing apparatus but with the capability of enlarging or reducing the image size. The composite television signal Si of the NTSC standards from the inlet first enters a decoder 6 which in turn produces three color signals R, G and B for red, green and blue as corresponding to the component television signals. These color signals R, G and B are then quantized by respective A/D (for analog/digital) converters 7.sub.R, 7.sub.G and 7.sub.B. The outputs of these converters in the form of digital signals are applied and stored as the picture elements to and in respective field memories 8.sub.R, 8.sub.G and 8.sub.B.
FIGS. 4(a) and 4(b) illustrate how the data X.sub.ij (i, j=1, 2, 3, . . . ) for the picture elements Pi (i=1, 2, 3, . . . ) are arrayed over one field in the aforesaid memories 8.sub.R, 8.sub.G and 8.sub.B. As shown in FIG. 4(a), for the picture elements P.sub.1, P.sub.2, P.sub.3, . . . , P.sub.910 from the first horizontal scanning line, the corresponding data X.sub.11, X.sub.12, X.sub.13, . . . with their components Rij, Gij and Bij of the colors R, G and B are written successively on the memories 8.sub.R, 8.sub.B and 8.sub.B respectively at their first rows. Then, in their second rows are written the data X.sub.21, X.sub.22, X.sub.23, . . . for the picture elements P.sub.911, P.sub.912, P.sub.913, . . . Here, the locations of the picture elements Pi in the entire area of the picture frame are indicated in FIG. 4(b). In the same figure, L.sub.K (k=1, 2, 3, . . . ,262) denotes the scanning line number.
Next, how to read the stored data out of the memories 8.sub.R, 8.sub.B and 8.sub.B is explained. An address generating circuit 9 produces outputs each representing a pattern of addresses indicated by a control circuit 10. Based on this pattern, one reaches the sequence of the data to be read from each of the field memories 8.sub.R, 8.sub.G and 8.sub.B. In the case when an enlarged picture of, for example, 2.times.2 times area is to be reproduced, the same data are read twice for either of the horizontal and vertical directions as shown in FIG. 5. As a result, for every one of the 4 (=2.times.2) picture elements at the corners of a square, one of which the picture element P.sub.1 shown in FIG. 4(b) occupies, the data (R.sub.11, G.sub.11, B.sub.11) which were written in connection with the picture element P.sub.2 are read out. Similarly, as to the next square to be placed on the right side, which includes the second picture element P.sub.2, the reading of the data (R.sub.12, G.sub.12, B.sub.12) which were written in connection with the picture element P2 is repeated 4 times successively. Subsequently, in a similar manner, the data of each of the remaining picture elements are read in allocation to the four corners of the corresponding one of the remaining squares. And, if necessary, any adjacent two of the picture elements are averaged by a signal processing circuit 11. During this time, the control circuit 10 takes the synchronism between the timings of reading of the above-described data and their computation. After that, by D/A (for digital/analog) converters 12.sub.R, 12.sub.G and 12.sub.B independent of one another for the individual signals of R, G and B, the above-described signals of R, G and B are returned back to the analog signals. In the next stage of an encoder 13, a composite television signal S.sub.0 in the duplicated form for the enlarged picture is produced at an outlet of the apparatus.
The foregoing is the common practice in the prior art of the video signal processing apparatus having the capabilities of enlarging and reducing the size of picture. Because an equal number of sets of the field memory and A/D and D/A converters to the number of components of the video signal are necessary; though the signal processing circuit for enlarging and reducing the size of picture can be constructed itself in simple form, the scale of the entirety of the apparatus becomes very large. Hence, an additional problem arose in that a desired reduction of the production cost of the apparatus was difficult to achieve.